The present invention relates in general to delta-sigma data converters, and, in particular, to data converters with digitally filtered pulse width modulation output stages and methods and systems using the same.
Delta-sigma modulators are particularly useful in digital to analog and analog to digital converters (DACs and ADCs). Using oversampling, the delta-sigma modulator spreads the quantization noise power across the oversampling frequency band, which is typically much greater than the input signal bandwidth. Additionally, the delta-sigma modulator performs noise shaping by acting as a lowpass filter to the input signal and a highpass filter to the noise; most of the quantization noise power is thereby shifted out of the signal band.
The typical delta sigma modulator includes a summer summing the input signal with negative feedback, a loop filter, a quantizer, and a feedback loop coupling the quantizer output and the inverting input of the summer. In a first order modulator, the loop filter includes a single integrator or other filter stage while the loop filter in a higher order modulator has a cascade of a corresponding number of filter stages. Higher-order modulators have improved quantization noise transfer characteristics over those of lower order, but stability becomes a more critical design factor as the order increases. The quantizer can be either a one-bit or a multiple-bit quantizer.
In DAC applications, such as low out-of-band noise DACs, continuous-time output stages, such as current summers, which convert the quantized modulator output into a relatively smooth analog signal have a number of advantages over discrete-time output stages, such as switched capacitor output stages. For example, in DAC systems in which the modulator output is quantized into a large number of levels (e.g. sixty-four or more levels represented by eight or more bits), continuous-time output stages are relatively easy to design and construct. In addition, continuous-time output stages operating on a large number of quantization levels are relatively immune to jitter and the problem of sampling of far out-of-band energy. These advantages make continuous-time output stages the best choice for integration into large digital chips. With respect to smaller data converters and coder-decoders (Codecs), avoiding the sampling of high frequency energy allows for the simplification of the clock management scheme.
Despite their advantages, continuous-time output stages are also subject to significant drawbacks, such as a susceptibility to inter-symbol interference. (Inter-symbol interference or ISI in this case is usually caused by asymmetry in leading and trailing edges of the output signals from continuous time elements or from analog memory, in which each symbol is dependent on the prior one.) ISI can dominate the noise and distortion components in the output analog stream of a continuous-time data converter, even if a large number of continuous-time conversion elements operate on data samples with a large number of quantization levels. While ISI can be minimized using return to zero (RTZ) techniques, RTZ techniques generally cause increased circuit sensitivity to the characteristics of the controlling clocks.
Therefore, improved circuits and methods are required which allow continuous-time output stages to be utilized in such applications as DACs while minimizing ISI and at the same time reducing the effects of clock characteristics on circuit performance.
According to one particular embodiment, a digital to analog converter is disclosed including a noise shaping modulator for modulating an input digital data stream, a plurality of output elements for generating a plurality of intermediate data streams from a modulated output stream from the modulator, and an output summer for summing the intermediate data streams to generate an output analog stream. The noise shaping modulator balances an edge transition rate of the output elements, such that the edge transition rate of two selected elements is approximately equal. By balancing the edge transition rate of the elements, the effects of ISI are largely eliminated.
Application of the present inventive principles provides for the design and construction of digital data converters, in particular DACs, utilizing continuous-time output elements with minimal susceptibility to ISI and clock vagaries. Generally, a duty-cycle modulator receives a digital input stream and generates a duty-cycle, pulse width modulated (PWM) encoded data stream. A finite impulse response (FIR) filter removes the fundamental frequency and harmonics of the PWM rate from the duty cycle modulated stream. By tapping the stages of the FIR filter with a plurality of digital to analog conversion elements, in either a continuous-time or discrete-time manner, an analog output signal is generated with reduced distortion due to jitter of ISI. In one particular embodiment, multiple pulse width modulator stages are interleaved in time to generate multiple time-overlapping PWM-encoded data streams. These overlapping PWM-encoded data streams drive multiple conversion elements with matched utilization and transition rates. A delta-sigma modulator with multiple attenuation bands in front of the interleaved PWM stages attenuates noise that would otherwise be demodulated by mismatch between the analog stages. A FIR filter coupled after each interleaved PWM stage removes out of band energy caused by the PWM process.